1. Field of the Invention
The present invention relates generally to the filed of semiconductor fabrication. More particularly, the present invention relates to a dummy cell pattern for filling a field between functional circuit blocks within a die. The invention is capable of unifying device performance, specifically in terms of ON current (ION) range between MOS transistors, within an integrated circuit die.
2. Description of the Prior Art
As known in the art, in semiconductor wafer fabrication, a rapid thermal anneal (RTA) process is often used to activate dopants, diffuse dopants, re-crystalize structures, etc. RTA processes are typically performed by utilizing halogen lamp-based heating equipment or lasers which direct radiation onto a wafer surface in order to change the wafer temperature.
During performance of these RTA processes, temperature variations occur at different points or areas within the integrated circuit die. Temperature variations within a die are due primarily to differences in thermal absorption and emission caused by different film stacks at different locations. As device dimensions shrink, the impact of these temperature variations has an increased effect on device performance by affecting electrical response or behavior at different locations within a die. Variations in device performance within a die have been observed and are attributed to temperature non-uniformity when the wafer (and its dies) undergoes front-side annealing schemes. These temperature variations not only result from differences in film stack materials, but also result from the pattern density across the die.
In semiconductor processing, dummy fill patterns have been used in diffusion mask and/or gate mask to prevent dishing effects from chemical-mechanical polishing (CMP) and to minimize the effects of device-to-device variations in pattern density. For example, in conventional shallow trench isolation processes, diffusion islands are isolated by oxide filled trenches. The formation of the shallow trench involves etching of the silicon trench patterns into a silicon substrate and subsequently filling the trenches with a thick oxide layer. The oxide layer is then planarized by using processes such as CMP, resist etchback, or oxide etchback processes. In these cases, the polish rate or etch rate is a function of the pattern density, which is defined as the percentage of the area that is occupied by diffusion patterns.
In order to ensure a uniform removal of the oxide over an entire wafer or substrate, the pattern density should ideally remain relatively the same over all areas. To achieve the relatively uniform pattern density, the field on the semiconductor substrate is often filled with dummy diffusion patterns. After filling with the dummy fill patterns, circuit areas and the field areas on the semiconductor substrate will have relatively similar pattern densities. However, the conventional dummy fill patterns deteriorate the variations in device performance within a die.
A semiconductor chip is typically formed by integrating up to millions or billions of transistors onto a single chip of semiconductor material. The uniformity of these transistors is generally of critical importance in the manufacturing of IC circuits. There is still a need for an improved fabrication process or method that is capable of unifying device performance and/or reducing temperature variations within an integrated circuit die.